Sigma-delta-based frequency synthesis

ABSTRACT

The present invention, generally speaking, satisfies the foregoing requirements using in combination within a frequency synthesis loop an SDM-based synthesizer and an SDM-based frequency digitizer. Since both blocks are SDM-based, the resulting signals can be differenced and filtered to produce a control signal for an oscillator. Low noise (and low spurs), fine frequency resolution and fast switching times may all be achieved simultaneously.

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No.09/624,574, filed Jul. 24, 2000, incorporated herein by reference, whichis a continuation-in-part of U.S. patent application Ser. No.09/268,731, filed Mar. 17, 1999, now U.S. Pat. No. 6,094,101.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to frequency synthesis.

2. State of the Art

In the field of communications, it is necessary to synthesize manydifferent frequencies, typically using a reference frequency or a smallnumber of reference frequencies. A phase lock look (PLL) is used forthis purpose.

The frequency to be synthesized and the reference frequency are notalways related by integer relations. Fractional-N synthesis may be usedin such instances. Originally, fractional-N synthesis (FNS) was used torefer to a technique in which an accumulator is used following aconventional divider. Upon accumulator rollover, the divider divides thesignal by the next highest integer on its subsequent cycle. Hence, thedivider divides the signal by N or N+1, with a duty cycle set by theaccumulator. The feedback signal to the phase detector is thereforefrequency modulated. A narrow PLL bandwidth averages the FM feedback toprovide fractional resolution (between 1/N and 1/(N+1)). The arrangementof a typical fractional-N synthesizer is shown in FIG. 1, where a block101 represents the combination divider/accumulator previously described.

More particularly, an output signal 103 of the divider/accumulator 101is applied to a phase/frequency detector (PFD) 105, together with areference frequency f_(ref). The PFD produces an error signal 107, whichis filtered using a low-pass filter 109 to produce a control signal 111for a VCO 113. The VCO produces an output signal f_(o), which is alsoapplied as the input signal to the divider/accumulator 101. The elementsof FIG. 1 may be grouped into a forward path 110 and a feedback path120. In the arrangement of FIG. 1, however, discrete spurious signalcomponents (“spurs”) are typically created in the output signal.

Fractional-N synthesis may also refer, more generally, to anynon-integer frequency division. One example is the use of a sigma-deltamodulator (SDM) to drive the modulus control inputs of a multi-modulusprescaler, as shown in FIG. 2. In FIG. 2, a forward path 210 includesthe same elements as in FIG. 1. In the feedback path 220, thedivider/accumulator of FIG. 1 is replaced by a multi-modulus prescaler221 controlled by a SDM 223. This technique also frequency modulates thefeedback to the phase detector. The FM rate is much higher than in theaccumulator method, so the PLL more readily averages the feedback.However, the noise component of the SDM does get through the PLL,appearing as a raised noise floor on the synthesizer output.

Both of the foregoing approaches provide finer frequency resolution thanconventional integer-N PLLs, or equivalently provide lower output noisefor identical resolution than integer-N PLLs. These advantages make FNSattractive. Still, the discrete spurs of the accumulator technique, orthe raised noise floor of the SDM technique, leave room for improvement.

A further technique is described in U.S. Pat. Nos. 4,965,533 and5,757,239. This technique, illustrated in FIG. 3, involves a directdigital synthesizer 301 followed by a PLL 303 set to a fixedmultiplication ratio, multiplying the DDS output (having relatively finefrequency resolution). A typical DDS arrangement is shown in FIG. 4. Anarithmetic circuit 410 comprises an adder 401 and an N-bit accumulator403 connected in the manner shown. In particular, an N-bit input value Mand the N-bit output of the accumulator 403 are applied to the adder401. The adder produces an N-bit result (excluding carry bit). Theaccumulator 403 is updated with the adder output in accordance withF_(CLK). The output value of the accumulator 403 is used to address aROM 405. The ROM 405 produces a digital value which is converted toanalog by a DAC 407 and low pass filtered using a LPF 409 to produce anoutput signal. The frequency of the output signal is that of F_(CLK)scaled by the ratio M:2^(N).

Using the technique of FIG. 3, spurious signals in the DDS output signalare either filtered by the PLL (if outside the PLL's bandwidth) ormultiplied by the PLL (if within its bandwidth). Thus, this technique isalso susceptible to noise degradation.

Although not widely known, a DDS-like arrangement can be operated as afirst-order SDM, as shown in FIG. 5. An arithmetic circuit 510 issimilar to the arithmetic circuit 410 of FIG. 4 except that a carry-outsignal c_(o) of the adder 501 is synchronized with f_(CLK) to form asignal c_(o)′, which is the desired SD waveform. As compared to theconventional DDS arrangement of FIG. 4, the SD waveform of FIG. 5 has aduty cycle of f_(o): f_(CLK), or M:2^(N).

In addition, a wideband frequency digitizer is described in U.S. Pat.No. 6,219,394 entitled DIGITAL FREQUENCY SAMPLING AND DISCRIMINATIONissued Apr. 17, 2001 and incorporated herein by reference. Asillustrated in FIG. 6, the wideband frequency digitizer 601 provides asigma-delta waveform representation 603 of the frequency ratio betweenits input signal f_(x) (605) and a reference F_(CLK) (607).

Despite the foregoing techniques, a need exists for a frequencysynthesis technique that simultaneously provides low noise (and lowspurs) while also providing fine frequency resolution and fast switchingtimes.

SUMMARY OF THE INVENTION

The present invention, generally speaking, satisfies the foregoingrequirements using in combination within a frequency synthesis loop anSDM-based synthesizer and an SDM-based frequency digitizer. Since bothblocks are SDM-based, the resulting signals can be differenced andfiltered to produce a control signal for an oscillator. Low noise (andlow spurs), fine frequency resolution and fast switching times may allbe achieved simultaneously.

BRIEF DESCRIPTION OF THE DRAWING

The present invention may be further understood from the followingdescription in conjunction with the appended drawing. In the drawing:

FIG. 1 shows the arrangement of a conventional fractional-N synthesizer;

FIG. 2 shows the use of a sigma-delta modulator (SDM) to drive themodulus control inputs of a multi-modulus prescaler;

FIG. 3 shows a synthesizer in which a direct digital synthesizer isfollowed by a PLL set to a fixed multiplication ratio, multiplying theDDS output;

FIG. 4 shows a typical DDS arrangement;

FIG. 5 illustrates a DDS-like arrangement operated as a first-order SDM;

FIG. 6 illustrates a wideband frequency digitizer that provides asigma-delta waveform representation of the frequency ratio between itsinput signal and a reference;

FIG. 7 illustrates a frequency synthesizer like that of FIG. 1,explicitly drawing attention to the asymmetry inherent in its operation;

FIG. 8 illustrates a frequency synthesizer like that of FIG. 2,explicitly drawing attention to the asymmetry inherent in its operation;

FIG. 9 illustrates a frequency synthesizer like that of FIG. 3,explicitly drawing attention to the asymmetry inherent in its operation;

FIG. 10 is a block diagram is shown of an exemplary embodiment of thepresent frequency synthesizer;

FIG. 11 shows a synthesizer using a WFD in which any offset produced bymoding is removed;

FIG. 12 shows a synthesizer like that of FIG. 11 but incorporating anoffset circuit; and

FIG. 13 is a diagram of an offset circuit suitable for use in thesynthesizer of FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is based in part on the recognition that the noiseproblems of the foregoing prior art techniques derive from the fact thatthe synthesizer phase detector (PD) is not operated symmetrically. Thatis, one PD input is jittered while the other is not. This asymmetry isindicated in FIG. 7, FIG. 8 and FIG. 9 (corresponding to FIG. 1, FIG. 2,and FIG. 3, respectively).

If instead both inputs to the PD are jittered by equivalent processes,their difference will ideally be zero, removing the noise otherwisecontributed by asymmetric operation.

Referring now to FIG. 10, a block diagram is shown of an exemplaryembodiment of the present frequency synthesizer. A DDS circuit 1001receives a clock input F_(CLK) and a control input M and produces asigma-delta output signal waveform DDS. The signal DDS is applied to adifference-forming circuit 1003 that produces as a difference signal asigma-delta waveform DIFF. The difference signal DIFF is filtered using,for example, a digital low-pass filter 1005. The filter output signal isconverted to analog using a DAC 1007 and applied to a VCO 1009, whichproduces an output signal f_(o).

The output signal f_(o) is applied to a WFD 1011, which produces asigma-delta output signal f_(b) based on applied reference f_(R). Thissignal is applied to an input of the difference-forming circuit 1003.

At lock, in terms of duty cycles, SD=f_(b); i.e., the stream of ones andzeros from the SD-DDS will be the same as the stream of ones and zerosfrom the WFD. Equating the expression for duty cycle for the DDS andWFD, and assuming F_(CLK)=f_(R), then$f_{0} = {M \cdot \frac{f_{C\quad L\quad K}}{2^{N}}}$

as in a conventional DDS. Thus, the circuit of FIG. 10 is functionallyinterchangeable with the ROM/DAC/LPF of a conventional DDS. The circuitof FIG. 10, however, offers the advantages of smaller size and lowerpower (although the use of feedback does impose some dynamic performancelimitations).

The WFD has an interesting further property that may be taken advantageof. Consider different frequency ranges, 0 to 1f_(R), 1f_(R) to 2f_(R),etc. When the input frequency is within the first range, the output ofthe WFD will be a stream of ones and zeros, the duty cycle varying frommostly zeros at lower frequencies within the octave and mostly ones athigher frequencies within the octave. When the input frequency is withinthe second range, the output of the WFD will be a stream of ones andtwos, the duty cycle varying from mostly ones at lower frequencieswithin the range and mostly twos at higher frequencies within the range,etc. The variation of the duty cycle, however, is essentially identicalwithin different octaves. One way to express this property is that theWFD “modes,” meaning that if f_(o)>f_(R), then there is an offset on thedigital signal of $ = {〚\frac{f_{o}}{f_{{r\quad {ef}}\quad}}〛}$

(the greatest integer) generated internally. If this offset is removed,(e.g., by taking only the least-significant bit from the WFD), then thedigital signal is the same as it would have been if the input frequencywere within the first range. A synthesizer in which the offset isremoved (by circuit 1101) is illustrated in FIG. 11.

The synthesizer of FIG. 11 offers a distinct advantage over asynthesizer using a conventional prescaler. Using a conventionalprescaler, because the synthesizer behaves as a multiplier, when theoutput frequency is changed but the modulation range is to remain thesame, the modulation control signal must be adjusted accordingly. In thesynthesizer of FIG. 11, the modulation control signal can remainunchanged, independent of the actual output frequency. That is, themodulation control signal need not be scaled according to outputfrequency as is the case with the use of frequency prescalers.

In the synthesizer of FIG. 11, the modulation control signal is thenumeric control signal M. Hence, if at a first output frequency,modulation is imparted by varying M within a predetermined range, thenat a second different output frequency, identical modulation may beimparted by varying M within the same predetermined range. The outputfrequency of the oscillator may be changed, for example, byincorporating within the feedback loop an offset circuit 1201 as shownin FIG. 12. One suitable offset circuit is shown in FIG. 13. The PLLacts to keep the output frequency of the offset circuit fixed; i.e., ifthe offset of the offset circuit is increased, then the frequency of theoscillator is increased by an equal amount. Similarly, if the offset ofthe offset circuit is decreased, then the frequency of the oscillator isdecreased by an equal amount.

Note that a prescaler may be used in place of the offset circuitpreviously described, although modulation scaling is then required.

It will be appreciated by those of ordinary skill in the art that theinvention can be embodied in other specific forms without departing fromthe spirit or essential character thereof. The presently disclosedembodiments are therefore considered in all respects to be illustrativeand not restrictive. The scope of the invention is indicated by theappended claims rather than the foregoing description, and all changeswhich come within the meaning and range of equivalents thereof areintended to be embraced therein.

What is claimed is:
 1. A method of frequency synthesis using anoscillator, comprising: using a first clock signal, generating a digitalsigma-delta-modulated reference signal; using a second clock signalhaving a frequency f_(R), generating a digital sigma-delta-modulatedsignal representation from an output signal of the oscillator;generating a difference signal responsive to the digitalsigma-delta-modulated reference signal and the digitalsigma-delta-modulated signal representation; filtering the differencesignal to form a filtered difference signal; and controlling theoscillator using the filtered difference signal.
 2. The method of claim1, wherein the digital sigma-delta-modulated signal representation has aduty cycle that varies identically within different frequency octaves ofthe output signal of the oscillator, said frequency octaves defined byfrequency ranges of f to (f+n*f_(R)), where f<f_(R), and n is anon-negative integer.
 3. The method of claim 2, further comprising: at afirst output frequency of said output signal, effecting modulation onthe output signal by varying a numeric control signal within apredetermined range; deriving from the output signal of the oscillator aderived signal having a first frequency; changing the frequency of thederived signal ; and effecting the same modulation on the output signalof the oscillator by varying the numeric control signal within the samepredetermined range.
 4. A frequency synthesizer comprising: anoscillator; means for generating a digital sigma-delta-modulatedreference signal; means for generating a digital sigma-delta-modulatedsignal representation from an output signal of the oscillator; means forgenerating a difference signal responsive to the digitalsigma-delta-modulated reference signal and the digitalsigma-delta-modulated signal representation; and a filter responsive tothe difference signal for generating a filtered difference signal, thefiltered difference signal being applied to the oscillator to controlthe oscillator.
 5. A circuit including a feedback loop for tracking aninput signal, comprising: an controlled oscillator; an error generatingcircuit; means for generating a digital reference signal having a dutycycle representing a frequency used to determine a predetermined outputfrequency of an output signal of the controlled oscillator; and afeedback circuit coupled to the controlled oscillator for generating adigital feedback signal having a duty cycle representing the frequencyof the output signal of the controlled oscillator; wherein the digitalreference signal and the feedback signal are applied to the errorgenerating circuit, which forms an error signal for controlling thecontrolled oscillator.
 6. The circuit of claim 5, wherein the means forgenerating a digital reference signal comprises a direct digitalsynthesizer.
 7. The circuit of claim 5, wherein the digital referencesignal is a digital sigma-delta waveform.
 8. The circuit of claim 5,wherein the feedback circuit comprises a frequency digitizer.
 9. Thecircuit of claim 8, wherein the frequency digitizer is responsive to theoutput signal to produce said digital feedback signal comprising adigital sigma-delta waveform representing the frequency of the outputsignal.
 10. The circuit of claim 9, wherein the digital sigma-deltawaveform representation has a duty cycle that varies identically withinfrequency octaves of the output signal, said frequency octaves definedby frequency ranges of to f+n*f_(R), where f<f_(R), and n is anon-negative integer.
 11. The circuit of claim 10, wherein the feedbackcircuit further comprises means for modifying the digital sigma-deltawaveform representation, when the frequency of the output signal iswithin a given octave, such that a resulting modified digitalsigma-delta waveform representation is the same as would be generated ifthe frequency of the output signal were within a different octave. 12.The circuit of claim 11, further comprising a frequency translationcircuit, for changing the output frequency of the controlled oscillatorto the feedback circuit.
 13. The circuit of claim 12, wherein thefrequency translation circuit comprises a prescaler.